Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/106068
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DC Field | Value | Language |
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dc.contributor.author | Ahn, C. | - |
dc.contributor.author | Shi, P. | - |
dc.contributor.author | You, S. | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | IEEE Signal Processing Letters, 2016; 23(5):600-604 | - |
dc.identifier.issn | 1070-9908 | - |
dc.identifier.issn | 1558-2361 | - |
dc.identifier.uri | http://hdl.handle.net/2440/106068 | - |
dc.description.abstract | In this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and H∞ performance. This DPLL is called the deadbeat H∞ FIR DPLL (DHFDPLL). The proposed DHFDPLL ensures the H∞ performance against incorrect information on noise and has intrinsic robustness against quantization effects because of the FIR structure. Demonstrative simulations are provided to show that the DHFDPLL exhibits excellent robustness against effects of incorrect noise and quantization compared with the existing DPLLs. | - |
dc.description.statementofresponsibility | Choon Ki Ahn, IEEE, Peng Shi, Sung Hyun You | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.rights | © 2016 IEEE. | - |
dc.source.uri | http://dx.doi.org/10.1109/lsp.2016.2542291 | - |
dc.title | A new approach on design of a digital phase-locked loop | - |
dc.type | Journal article | - |
dc.identifier.doi | 10.1109/LSP.2016.2542291 | - |
pubs.publication-status | Published | - |
dc.identifier.orcid | Shi, P. [0000-0001-8218-586X] | - |
Appears in Collections: | Aurora harvest 8 Electrical and Electronic Engineering publications |
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