Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/109131
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DC Field | Value | Language |
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dc.contributor.author | Ahn, C. | - |
dc.contributor.author | Shi, P. | - |
dc.contributor.author | Hyun You, S. | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | IEEE Signal Processing Letters, 2016; 23(12):1844-1847 | - |
dc.identifier.issn | 1070-9908 | - |
dc.identifier.issn | 1558-2361 | - |
dc.identifier.uri | http://hdl.handle.net/2440/109131 | - |
dc.description.abstract | This letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs. | - |
dc.description.statementofresponsibility | Choon Ki Ahn, Peng Shi, Sung Hyun You | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.rights | © 2016 IEEE. | - |
dc.source.uri | http://dx.doi.org/10.1109/lsp.2016.2623520 | - |
dc.subject | Digital phase-locked loop (DPLL); moving average; optimal memory size; robustness; unbiasedness | - |
dc.title | Optimal memory size formula for moving-average digital phase-locked loop | - |
dc.type | Journal article | - |
dc.identifier.doi | 10.1109/LSP.2016.2623520 | - |
dc.relation.grant | 61573112 | - |
dc.relation.grant | U1509217 | - |
dc.relation.grant | http://purl.org/au-research/grants/arc/DP140102180 | - |
pubs.publication-status | Published | - |
dc.identifier.orcid | Shi, P. [0000-0001-8218-586X] | - |
Appears in Collections: | Aurora harvest 8 Electrical and Electronic Engineering publications |
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