Threshold logic based implementation of high performance VLSI arithmetic circuits

Abstract

This Thesis focuses on the area of high speed very large scale integration (VLSI) complementary metal oxide semiconductor (CMOS) circuit design using threshold logic (TL) techniques. The work described in this document contributes three major advances on high speed TL based CMOS circuit design: (i) the development and experimental verification of novel high speed TL gate circuit topologies; (ii) a method for delay modelling of sense-amplifier based TL gates and (iii) novel TL based networks for the implementation of high speed arithmetic circuits. In this Thesis, the basics and previous work in threshold logic are reviewed, including theoretical results for TL based networks used in arithmetic and TL gate circuit design techniques. Novel floating gate based TL circuit implementations based on precharged sense-amplifiers employing charge recycyling are described and experimentally verified. A new weight-shared circuit technique is proposed which significantly reduces the area cost. Based on the theory of Logical Effort, a model for the Charge Recycling Threshold Logic (CRTL) gate is developed and experimentally verified. This model is used to evaluate and compare a number of CRTL based circuits, demonstrating its significant reduced delay compared to conventional static and dynamic CMOS logic. New parallel counters are proposed and partial product reduction trees based on these counters for use in parallel multipliers are shown to be significantly faster than previously published schemes. The 64-bit prefix-8 adder presented here is the fastest 64-bit adder published to date. The contributions in this Thesis are an important step towards alleviating the issues faced in present day VLSI arithmetic design and demonstrate for the first time the significant benefits offered by TL compared to conventional logic circuit techniques. The methodologies introduced are shown to lead to increased circuit compactness and reduced power dissipation which are of particular interest for future smart sensor technology and will potentially impact on future portable electronics systems for a range of applications from mobile personal communications through to aerospace systems.