Dynamic bootstrapped shift register for smart sensor arrays

Abstract

In this paper we demonstrate the operation of a dynamic serial-to-parallel shift register, with only four transistors per stage. A bootstrap capacitor is used to overcome the problem of transistor threshold voltage drop. We will refer to this new logic family as non-ratioed bootstrap logic (NRBL). Simulation results are presented showing the operation of the shift register along with Monte Carlo analysis to demonstrate the robustness of the circuit. A key application area for this novel shift register is in the addressing and read out of high-density smart sensor arrays.