New efficient offset voltage cancellation techniques using digital trimming

Abstract

Operational amplifiers have an important role as a basic building block in analog circuit design. One of the performance limitations of these circuits is the input referred offset voltage or simply input offset voltage. This voltage can range between 1 - 30 mV depending on the fabrication process and the sizes of the ideally symmetrical input transistors of the differential amplifier. Two new techniques to digitally trim the offset voltage of operation amplifier are presented and discussed. The techniques can be divided into two categories. The first is called weighted current technique, while the second is called weighted voltage technique. The attractive features of the new techniques are the trimming is performed digitally, large dynamic range; require small silicon area, and the ability to provide auto-zero cancellation using extra hardware. In the presented analysis, a binary weighted scheme will be used. However, the techniques are not restricted to that scheme and they are still applicable with other weighting schemes. A detailed analysis of these techniques will be presented and discussed and measurement from fabrication and simulation will be presented.