Sub-5.5 FO4 delay CMOS 64-bit domino / threshold logic adder design

Abstract

This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor leveldelay estimation. The adder is a hybrid design, consisting of dominologic and the recently proposed Charge Recycling Threshold Logic(CRTL). The delay evaluation is based LE modeling of the delay ofthe domino and CRTL gates. From the initial estimations, the 8-bitsparse carry look-ahead/carry-select scheme has a delay of less than5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 FO4delay faster than any previously published domino design.