Delay evaluation of high speed data-path circuits based on threshold logic

Abstract

The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold logic. The designs include 8 to 64-input AND, 4-bit carry generate, and the carry-out of a (7,3) parallel (population) counter. The circuits are designed using both domino gates and the recently proposed CMOS Charge Recycling Threshold Logic (CRTL). It is shown that compared to domino, the CRTL design examples are typically between 1.3 and 2.7 times faster over a wide range of load values, while presenting the same input capacitance to the driver.