Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/30003
Type: Book chapter
Title: A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions
Author: Celinski, P.
Sherman, G.
Lopez, J.
Abbott, D.
Citation: Advances in Neural Networks and Applications, 2001 / Nikos Mastorakis, (ed./s), vol.4236, pp.224-228
Publisher: World Scientific Publishing
Publisher Place: 222 Rosewood Dve, Danvers, Ma 01923, USA
Issue Date: 2001
ISBN: 9608052262
Editor: Nikos Mastorakis,
Abstract: The main result of this paper is the development of a systematic paper-and-pencil design methodology for implementing Boolean functions of up to 4 variables using threshold logic (TL) gates, which does not require linear programming, for the first time. The methodology is similar in operation to the Karnaugh map logic minimization technique, and is based on determining the minimum threshold cover of a Boolean function. The paper also reviews aspects of TL and illustrates the application of the proposed design methodology to VLSI design using the neuron-MOS technique.
Appears in Collections:Aurora harvest 2
Electrical and Electronic Engineering publications

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