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https://hdl.handle.net/2440/40075
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Type: | Conference paper |
Title: | An open source synthesisable model in VHDL of a 64-bit MIPS-based processor |
Author: | Kelly, D. Phillips, B. Al-Sarawi, S. |
Citation: | Smart Structures, Devices, and Systems III: 11-13 December 2006, Adelaide, Australia / Said F. Al-Sarawi (ed.):pp.641411 1-9 |
Publisher: | SPIE |
Publisher Place: | USA |
Issue Date: | 2007 |
Series/Report no.: | Proceedings of SPIE: the International Society for Optical Engineering ; 6414 |
ISBN: | 0819465232 9780819465221 |
ISSN: | 0277-786X 1996-756X |
Conference Name: | Smart structures, devices, and systems III (2006 : Adelaide, Australia) |
Editor: | Al-Sarawi, S. |
Statement of Responsibility: | Daniel R. Kelly, Braden J. Phillips, and Said Al-Sarawi |
Abstract: | This report describes an open source VHDL description of a 64-bit MIPS-based processor. The pipeline can execute most instructions from the MIPS III instruction set architecture (ISA). The full pipeline is made available to digital VLSI engineers as a platform to test cell designs as a part of a complete computing system. The pipeline is an 8-stage RISC based on the MIPS R4000 series of processors, and includes common arithmetic operations on 32- and 64-bit operands, and full IEEE 754 floating point support. This report describes the architecture and components of the MIPS-based processor. |
Description: | Copyright © 2007 SPIE - The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. |
Provenance: | Published online Jan. 11, 2007. |
DOI: | 10.1117/12.695580 |
Published version: | http://dx.doi.org/10.1117/12.695580 |
Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications |
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