Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/40078
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Type: | Conference paper |
Title: | Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach |
Author: | Celenski, P. Al-Sarawi, S. Abbott, D. Cotofana, S. Vassiliadis, S. |
Citation: | IEEE Computer Society Annual Symposium on VLSI : proceedings : Emerging trends in VLSI systems design : 19-20 February, 2004, Lafayette, Louisiana / Asim Smailagic and Magdy Bayoumi (eds.):pp.127-132 |
Publisher: | IEEE Computer Society |
Publisher Place: | Online |
Issue Date: | 2004 |
Series/Report no.: | IEEE Computer Society Annual on VLSI |
ISBN: | 0769520979 9780769520971 |
ISSN: | 2159-3477 2159-3477 |
Conference Name: | IEEE Computer Society Symposium on VLSI (2004 : Lafayette, Louisiana) |
Editor: | Smailagic, A. Bayoumi, M. |
Statement of Responsibility: | Peter Celinski, Said Al-Sarawi, Derek Abbott, Sorin Cotofana and Stamatis Vassiliadis |
Abstract: | This paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gates based on systematic transistor level delay estimation using Logical Effort (LE). The adders are hybrid designs consisting of domino and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, we select the 8-bit sparse carry look-ahead/carry-select scheme. Simulations indicate a delay of less than 5 FO4, which is 1.1 FO4 or 17% faster than the nearest domino design. |
Description: | Copyright © 2004 IEEE |
DOI: | 10.1109/ISVLSI.2004.1339519 |
Published version: | http://dx.doi.org/10.1109/isvlsi.2004.1339519 |
Appears in Collections: | Aurora harvest Electrical and Electronic Engineering publications |
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hdl_40078.pdf | 160.69 kB | Publisher's PDF | View/Open |
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