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https://hdl.handle.net/2440/72131
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Type: | Conference paper |
Title: | Utility-based dynamic cache resizing |
Author: | Tian, G. Liebelt, M. |
Citation: | Proceedings of the International Conference on Computer Science and Network Technology (ICCSNT), held in Harbin, China, 24-26 December, 2011: pp.610-616 |
Publisher: | IEEE |
Publisher Place: | CD |
Issue Date: | 2011 |
ISBN: | 9781457715860 |
Conference Name: | International Conference on Computer Science and Network Technology (2011 : Harbin, China) |
Statement of Responsibility: | Geng Tian and Michael Liebelt |
Abstract: | Continuing increases in transistor density are enabling increases in the number of on-chip cores and the size of caches. However very large caches in future systems might not be fully utilised. Under-utilised active caches result in a waste of static power. Off-line profiling of applications to determine optimal cache size and configuration is not practical. As an alternative we propose a simple scheme with limited hardware overhead, to dynamically evaluate the utility of the last level cache slice on each tile and to tune the cache associativity at tile-level granularity. In simulations our tuning scheme achieved an average of 30% of static power saving with a slight 0.6% degradation of IPC. |
Keywords: | Static power saving cache multithreading tiled structure power gating |
Rights: | © 2011 IEEE |
DOI: | 10.1109/ICCSNT.2011.6182032 |
Published version: | http://dx.doi.org/10.1109/iccsnt.2011.6182032 |
Appears in Collections: | Aurora harvest Electrical and Electronic Engineering publications Environment Institute publications |
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