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https://hdl.handle.net/2440/90088
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Type: | Conference paper |
Title: | Digital RF processing system for Hardware-in-the-Loop simulation |
Author: | Piyaratna, S. Duong, N. Carr, J. Bird, D. Kennedy, S. Udina, A. Jenkinson, P. |
Citation: | 2013 International Conference on Radar - Beyond Orthodoxy: New Paradigms in Radar, RADAR 2013, 2013, pp.554-559 |
Publisher: | IEEE |
Issue Date: | 2013 |
ISBN: | 9781467351775 |
Conference Name: | 2013 International Conference on Radar (9 Sep 2013 - 12 Sep 2013 : Adelaide, South Australia) |
Statement of Responsibility: | Sanka Piyaratna, Ninh Duong, Joel Carr, David Bird, Stephen Kennedy, Andrew Udina, Patrick Jenkinson |
Abstract: | This paper presents the design of the Digital RF Processing (DRFP) system for generating many of the RF effects within the Advanced Radar Environment Simulator (ARES) Hardware-in-the-Loop system developed within the Hardware-in-the-Loop Technology and Simulation Group (HTS) of Weapons Systems Division (WSD), DSTO. This system is based on Digital RF Memory (DRFM) technology. The DRFM signal processing is performed on a digitised signal on a commercial-off-the-shelf (COTS) Field Programmable Gate Array (FPGA) hardware board. The RF Up/Down conversion is performed by a COTS RF module. The RF up/down converter translates an 800MHz instantaneous band in range 2-18 GHz down to 500 MHz IF signal (100 - 900 MHz). The ARES Digital RF Processor (DRFP) provides the technique designer with a set of tools to model a number of environmental effects, such as Doppler, Range Delay, intra-pulse complex modulations, and multi-point convolutions. The ARES DRFP provides a real-time communication link to receive high fidelity generic environmental parameters which are computed by a numerical model of the radar environment. This feature provides the technique designer with significant flexibility compared to other typical Radar/RF scene generators. This paper discusses the implementation details and the design strategies of the development. Preliminary results of the ARES DRFP output are also discussed. |
Keywords: | Digital RF Memory (DRFM); Field Programmable Gate Array (FPGA); Hardware-in-the-Loop (HWIL |
Rights: | © 2013 Commonwealth of Australia |
DOI: | 10.1109/RADAR.2013.6652048 |
Published version: | http://dx.doi.org/10.1109/radar.2013.6652048 |
Appears in Collections: | Aurora harvest 2 Electrical and Electronic Engineering publications |
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