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Issue Date
Title
Author(s)
2001
Low power, high speed, charge recycling CMOS threshold logic gate
Celinski, P.
;
Lopez, J.
;
Al-Sarawi, S.
;
Abbott, D.
2001
A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions
Celinski, P.
;
Sherman, G.
;
Lopez, J.
;
Abbott, D.
;
Mastorakis, N.
;
WSES International Conference (11 Feb 2001 : Tenerife, Canary Islands, Spain)
2001
A low power, high speed threshold logic and its application to the design of novel carry lookahead adders
Celinski, P.
;
Lopez, J.
;
Al-Sarawi, S.
;
Abbott, D.
;
Bergmann, N.W.
;
Electronics and Structures for MEMS II (2nd : 2001 : Adelaide, Australia)
2001
A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions
Celinski, P.
;
Sherman, G.
;
Lopez, J.
;
Abbott, D.
;
Nikos Mastorakis,
Discover
Author
4
Celinski, P.
2
Al-Sarawi, S.
2
Sherman, G.
1
Bergmann, N.W.
1
Electronics and Structures for ME...
1
Mastorakis, N.
1
Nikos Mastorakis,
1
WSES International Conference (11...