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Preview	Issue Date	Title	Author(s)
	2001	Low power, high speed, charge recycling CMOS threshold logic gate	Celinski, P.; Lopez, J.; Al-Sarawi, S.; Abbott, D.
	2002	Compact parallel (m,n) counters based on self-timed threshold logic	Celinski, P.; Lopez, J.; Al-Sarawi, S.; Abbott, D.
	2004	Delay evaluation of high speed data-path circuits based on threshold logic	Celinski, P.; Abbott, D.; Cotofana, S.; Macii, E.; Paliouras, V.; Koufopavlou, O.; PATMOS 2004 (14th : 2004 : Santorini, Greece)
	2001	A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions	Celinski, P.; Sherman, G.; Lopez, J.; Abbott, D.; Mastorakis, N.; WSES International Conference (11 Feb 2001 : Tenerife, Canary Islands, Spain)
	2003	Level sensitive latch	Celinski, P.; Abbott, D.; Al-Sarawi, S.; Luminus PTY Ltd (US)
	2001	A low power, high speed threshold logic and its application to the design of novel carry lookahead adders	Celinski, P.; Lopez, J.; Al-Sarawi, S.; Abbott, D.; Bergmann, N.W.; Electronics and Structures for MEMS II (2nd : 2001 : Adelaide, Australia)
	2001	A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions	Celinski, P.; Sherman, G.; Lopez, J.; Abbott, D.; Nikos Mastorakis,
	2003	State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications	Celinski, P.; Cotofana, S.; Lopez, J.; Al-Sarawi, S.; Abbott, D.; Lopez, J.F.; Montiel Nelson, J.A.; Pavlidis, D.; VLSI Circuits and Systems Conference (2003 : Gran Canaria, Spain)
	2004	Sub-5.5 FO4 delay CMOS 64-bit domino / threshold logic adder design	Celinski, P.; Cotofana, S.; Al-Sarawi, S.; Abbott, D.; Faraone, L.; Varadan, K.; Microelectronics, MEMS, and Nanotechnology (2003 : Perth, Australia)
	2002	Threshold logic parallel counters for 32-bit multipliers	Celinski, P.; Cotofana, S.; Abbott, D.; Harvey, E.C.; Abbott, D.; Varadan, V.K.; International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia)